Network packets normally comprise a sequence of 8-bit octets. In order to allow high data transfer rates, it is desirable for a DMA system to transfer data in larger units. Thus, data paths between a DMA and a buffer memory, and the DMA and a First In-First Out (FIFO) buffer, are one ‘word’ wide. The DMA generally reads only whole words from the memory and only words that are properly aligned to word boundaries (e.g. words whose octet addresses are a multiple of four (or other multiple)).
In a buffer memory, a packet may contain an arbitrary number of octets and may be incompatible with word access in a variety of ways. For example, the packet may be badly aligned in memory. In another example, the packet may not start on a word boundary (e.g., a start address may not be a multiple of four). Therefore, when the DMA reads the word containing the first octet, it will also receive one or more unwanted octets.
The packet data may not be contiguous in memory and may be held as several fragments with arbitrary alignments and arbitrary sizes (not necessarily a multiple of the word size). This is a common situation where the processor is transferring packets received from another source. The transfer may involve changing the packet's protocol encapsulation by adding and/or removing octets to/from the start and end of the packet, while preserving the payload data in the middle of the packet. It is expensive to achieve this while keeping the whole packet contiguous in memory (as it may need to be copied to a new, larger buffer). An alternative is to represent the packet as a list of fragments (e.g. header, payload, trailer) in separate memory buffers.
The processor may also need to perform protocol conversion which involves inserting a small number of octets into an existing packet. Examples of this may include priority and Virtual Local Area Network (VLAN) tags in Ethernet standards 802.1p and 802.1q. However, it is generally unduly expensive to achieve this by manipulating memory buffers and copying data.
Therefore, there is a need for a more efficient method and system for implementing a DMA scheduling mechanism and a DMA system for transmission from fragmented buffers.